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Chaired by: Nick McKeown, Stanford University; Jen Rexford, Princeton University.
Sponsored by: Netronome, Microsoft, Intel, Cisco & Barefoot Networks.
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Yale University, Andreas Vollemy
Demo: Magellan: Mapping Algorithmic Policies to P4 Dataplanes (Poster)
  The Algorithmic Policies (AP) SDN programming model provides a simple,familiar and expressive model for programming the behavior of both individual packet processing devices as well as network-wide packet processing behavior. The algorithmic policy model is simple for programmers, because it eliminates elements that are unnecessary in describing the input-output behavior, such as tables, matches, and actions. It is familiar, because it largely provides the same constructs of ordinary programming languages. It is expressive because it provides constructs such as complex data structures and loops.
   On the other hand, effectively utilizing P4-accessible resources from algorithmic policies can be extremely challenging, because APs are expressed in a general-purpose programming language with arbitrary complex control structures and the control structures of APs can be completely oblivious to the existence of multi-tables. Hence, it is not clear at all whether one can effectively program multi-table pipelines from such APs.
  This demo will present the architecture of Magellan, a compiler and runtime system that effectively compiles algorithmic policies to P4 pipelines and corresponding runtime controllers for the generated pipelines. The demo will present system architecture as well as algorithms for compiling APs to efficient pipeline designs and proactive runtime controllers.

Xilinx, Gordon Brebner
Demo: Programmable Target Architectures for P4 (Poster)
   The original P4 language design featured a specified switch architecture, with some components P4-programmable and others not.  The evolution of P4 involves a separation of the core language features from target architecture specification, so that P4 is used to describe packet processing components which then drop into specific (and non P4-described) architectures.  This demonstration will consider the new approach from the architecture direction: where a programming language is used to describe an architecture instance, and then compilation of this generates P4 specs needed to describe (a) the P4 components that will be dropped into the architecture instance; and (b) library methods that will be available for use by the P4 components.  Overall compilation involves generation of a complete system implementation that incorporates implementations of the P4 components.  This will be illustrated by a prototype Xilinx compilation flow that generates such systems with an FPGA implementation, given an architecture description and included P4 component descriptions as input.      The demonstration will show a working system implemented using the flow, running at 100Gb/s line rate on a Xilinx Ultrascale communications board.

VMware, Mukesh Hira & Barefoot Networks, Jithin Thomas
Demo: Inband Network Telemetry - Improving Network Monitoring and Management with Programmable Data Planes, (Poster)
   Inband Network Telemetry (“INT”) is a framework designed to allow the collection and reporting of network state, by the data plane, without requiring intervention or work by the control plane.  In the INT architectural model, packets contain header fields that are interpreted as “telemetry instructions” by network devices.  These instructions tell an INT-capable device what state to collect and write into the packet as it transits the network.  SwitchID, hop latency and  queue occupancy are some of the per-packet metadata that could be collected using INT. This demo illustrates a real-time network monitoring application that utilizes INT to monitor the path and latency of each connection in a network.  The application utilizes end-host based VXLAN-GPE encapsulation to transport INT data, which is aggregated at a centralized monitor process and then visualized in a web-client.

USC, Rui Miao & Barefoot Networks, JK Lee
Demo: Adding L4 Load-Balancing to Every Switch, (Poster)
   Layer-4 server load balancing is critical to provide high availability and auto-scaling to services running in clouds. Any L4 load-balancing solutions must ensure per-connection consistency: a capability to forward all the packets of a connection to the identical server even when the pool of servers backing the load-balanced virtual address keeps changing over time. This requirement leads to maintaining a huge amount of state in the data plane to track tens of millions of concurrent connections. To meet all these challenging requirements, cloud operators today use software-based load balancers running on commodity servers, as opposed to dedicated hardware middle-boxes, but this S/W-based approach suffers from high latency, low per-server processing capacity, and high cost.
   In this work, we propose to embed the L4 load balancing functionalities directly on network switches. To maintain millions of connections on low-cost merchant-grade switches' on-chip memory, we implement digest-based Cuckoo hashing across switch control & data planes, processing up to 10M concurrent connections at line-rate. Careful design of hashing with the use of Bloom Filter ensures per-connection consistency. We demo our prototype L4 load-balancer built in P4.

UMass Lowell, Swaroop Thool
Demo: Sketch: Network Measurement in P4 - Identify Heavy Hitter Flows with Software Defined Measurement (Poster)
Network measurement is critical for understanding network usage patterns, tuning the performance of networks, and troubleshooting network issues. One of the important measurement tasks is to identify heavy-hitter flows that take a significant portion of network bandwidth. This becomes increasingly challenging as the line rates scales exponentially, making the storage of network traces and offline analysis infeasible. To address this challenge, prior work has used “sketch”, a compact data structure with provable properties on analyzing streaming data like network flows.
We focus on the Count-Min (CM) sketch that relies on a counter matrix to estimate the traffic volume of flows, and rank the flows in an  ascending order. We have implemented a CM sketch using P4, and integrated it into the “simple_router” reference design. The implementation of CM sketch consists of overall 475 lines of P4 code. We have verified the correctness of the design by testing with synthetic network flows generated in mininet. We extend the design with a new debugging and verification methodology (based on using copy_to_cpu()).
We make several contributions in this work: (1) we are the first to demonstrate the design of network measurement sketch in P4, which can be readily leveraged in P4 based network switches and middleboxes; (2) This work extends example P4 applications with a different category, which requires substantial metadata processing; and (3) by introducing a special debug packet called “D-packet”, we enhance the debugging support to the existing P4 tool chain, facilitating the design of new applications among the P4 community.

Princeton, Muhammad Shahbaz
Demo: OVS Datapath Specialization Using P4 (Poster)
Unlike OpenFlow, which provides a pipelined match-action table (MAT) abstraction, the native Open vSwitch (OVS) itself, on the other hand, provides a pool of MATs for the user to program. There is no inherent notion of a pipeline and it’s the responsibility of the user to not only maintain tables’ state but also explicitly construct the pipeline by installing carefully crafted flow rules at runtime. This abstraction, though very powerful, makes it hard to manage the switch as the number of MATs increase. P4 helps solve this problem by enabling users to statically define MAT pipelines as P4 programs and letting them only manage the tables’ state at runtime. This has many benefits and, furthermore, with a P4 program one can also specialize OVS to implement only the required features like parsing Ethernet headers and not IP headers in case of layer2 forwarding. In this demo, we will showcase our P4 compiler for OVS and demonstrate how OVS can be specialized using P4.

Polictecnico di Milano, Davide Sanvito
Demo: P4 Implementation of a Stateful Data Plane and its Application for Failure Resiliency (Poster)
   This demo presents a P4 implementation of OpenState, a stateful pipeline design (originally developed as an OpenFlow extension), that allows packets to be forwarded on the basis of “flow-states”, maintained and updated by the fast path itself as a consequence of packet-level events (i.e. table match) and timers. The demo presents an application for failure resiliency that exploits the fast adaptation of the forwarding behavior in the data path. This application provides i) a programmable detection mechanism based on switches’ periodic link probing and ii) a fast reroute of traffic flows even in case of distant failures, regardless of controller availability. It can guarantee short (i.e. few ms) failure detection and recovery delays, with a configurable trade off between overhead and failover responsiveness.

Netronome, David George & Johann Tönsing
Demo: P4 Programmable Telemetry Platform: COTS Server Accelerated by Intelligent NIC
Commodity servers are being used as platforms for Network Functions Virtualization (NFV) applications. While the networking functionality in such platforms could be programmed using software in traditional programming languages, programmer productivity can be increased by employing domain specific programming languages like P4. By offloading the execution of the P4 program to an intelligent network interface card (iNIC), the resulting system can offer increased scalability as well, e.g. more Virtual Network Function (VNF) instances per server and/or higher throughput can be supported. This is demonstrated by editing and debugging P4 programs in an Integrated Development Environment, compiling P4 programs to the native code of a iNIC designed for standard 1RU COTS servers, and running a P4 application to perform custom tunnel / telemetry processing while steering traffic to VNFs running in the iNIC equipped server.

MIT, Anirudh Sivaraman
Demo: Packet Transactions: A Programming Model for Dataplane Algorithms at Hardware Speed (Poster)
Data-plane algorithms execute on every packet traversing a network switch; they encompass many schemes for congestion control, network measurement, active-queue management, and load balancing. Because these algorithms are implemented in hardware today, they cannot be changed after being built. To address this problem, recent work has proposed designs for programmable line-rate switches. However, the languages to program them today closely resemble the underlying hardware,making them inconvenient for this purpose.
This paper presents Domino, a C-like imperative language to express data-plane algorithms. Domino introduces the notion of a packet transaction, defined as a sequential code block that is atomic and isolated from other such code blocks. The Domino compiler compiles Domino code to P4, an emerging language for programmable switches. We show how Domino enables several data-plane algorithms written in C syntax to run at hardware line rates.

Intel, Dan Daly
Demo: P4 Defined 25G/100G Ethernet Adapters: Using P4 on the Server to Define In-Line Network Acceleration
This demonstration uses Intel® FM10000 based Ethernet adapters on standard high volume servers to accelerate workloads running over network virtualized infrastructure.  When using 25G/100Gb Ethernet systems running at these increased data rates can benefit from accelerations within the server platform and accelerations within each multi-core application.  P4 is used to describe acceleration capabilities offered by the platform to both the virtual switch and to virtualized applications running DPDK (Data Plane Developer Kit).

Huawei Technologies, Yunsong Lu
Demo #1: rSwitch: Redesigned Network Switch - Fully Programmable Virtual Switch Designed for Cloud, SDN, and NFV
The demo will be include high-performance software data path, which saturate 40Gb Ethernet with minimum CPU consumption, and with hardware acceleration, more CPU will be saved for applications.

Huawei Technologies, Haoyu Song
Demo #2: Using P4 to Program an NP-based POF Router (Poster)
   In this demo we will use the applications published by P4 consortium. The applications will be compiled by the open source P4 front-end compiler into HLIR and our P4-POF module will further translate HLIR into JSON commands and feed them into the POF controller through REST API. The POF controller then emits corresponding POF messages to the NE40E router so the router is programmed. We’ll use an Ethernet tester to generate and receive traffic to show the router works as described by the  P4 program.

Concordia University, Samar Abdi
Demo: Targeting P4 to Network Processor Models - Fast Simulation of P4 Applications on Programmable Forwarding Plane Architectures (Poster)
Network processors are widely used as programmable alternatives to fixed function switches, particularly in edge routers. A typical network processor chip consists of several RISC cores, hardware accelerators and heterogeneous memories, interconnected with complex on-chip communication architecture. Network processor simulation models are of interest to both chip designers and network equipment vendors who integrate such chips in their products. We have developed a framework for high speed transaction-level simulation of network processor architectures that enables their functional validation and performance evaluation early in the design cycle. The integration with P4 enables the designer to configure our network processor models from a given P4 application. To accomplish this, we re-target the publicly available soft-switch P4 compiler to our model by separating the parsing module to configure the programmable parser in the network processor model, and the table-flow graph to program the RISC core models. We have also re-implemented the search and look-up data structures on top of our memory models in order to accurately capture the memory transactions during the P4 application execution. In this demonstration, we will show the execution of sample P4 applications on our network processor models, as well as the performance implications of changing the architectural parameters of the network processor.

Cornell University, Han Wang 
Demo: Open Source P4 Backend for FPGA (Poster)
   We present P4FPGA, an open source compiler backend to generate FPGA dataplane pipeline from P4. Instead of using Verilog, Our compiler generates Bluespec System Verilog, a high-level hardware description language with language features that greatly simplifies the design of compiler backend. In addition to generating dataplane code, P4FPGA compiler backend also generates control plane APIs to implement control channels between network controllers and FPGA dataplane. The generated dataplane and control plane APIs can be simulated simultaneously using native Bluespec cycle- accurate simulator. The generated Bluespec code is vendor-agnostic and can be compiled to different FPGA platforms, such Xilinx’s NetFPGA-SUME and Altera’s DE5-Net. As demonstration, we will show how parser, match/action pipeline, queues can be implemented in Bluespec and generated from P4FPGA backend. We will further show an example application which exercises the generated dataplane pipeline and control plane APIs. P4FPGA bridges the implementation gap from high-level declarative dataplane language to low-level hardware implementation on FPGA. We envision it to be used for experimenting and prototyping customized NIC and switch dataplane and novel queueing mechanisms.

Corsa Technology, Ben Mack-Crane & Peter Musgrave
P4 on Corsa Hardware: Using P4 to Configure Pipelines on Corsa Hardware (Poster)
   Corsa Technology develops programmable, flexible hardware for SDN. In this demonstration two very different packet processing P4 programs will be shown running on an identical hardware configuration. First, a layer 2/3 packet prioritization application with DSCP remarking and metering will be shown. Second, a L3/L4 application that performs DSCP remarking of DNS packets and provides a destination IP blacklist will be shown.  These demonstrate the utility of describing packet processing in P4 and the ability of the Corsa solution to run both programs without hardware configuration change.