2nd P4 Workshop by Stanford/ONRC

The original P4 language design featured a specified switch architecture, with some components P4-programmable and others not.  The evolution of P4 involves a separation of the core language features from target architecture specification, so that P4 is used to describe packet processing components which then drop into specific (and non P4-described) architectures.  This talk will consider the new approach from the architecture direction: where a programming language is used to describe an architecture instance, and then compilation of this generates P4 specs needed to describe (a) the P4 components that will be dropped into the architecture instance; and (b) library methods that will be available for use by the P4 components.  Overall compilation involves generation of a complete system implementation that incorporates implementations of the P4 components.  The approach will be illustrated by a prototype Xilinx compilation flow that generates such systems with an FPGA implementation, given an architecture description and included P4 component descriptions as input.