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Chaired by: Nick McKeown, Stanford University; Jen Rexford, Princeton University.
Sponsored by: Netronome, Microsoft, Intel, Cisco & Barefoot Networks.
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Wednesday, November 18 • 2:15pm - 2:30pm
Programmable Target Architectures for P4

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The original P4 language design featured a specified switch architecture, with some components P4-programmable and others not.  The evolution of P4 involves a separation of the core language features from target architecture specification, so that P4 is used to describe packet processing components which then drop into specific (and non P4-described) architectures.  This talk will consider the new approach from the architecture direction: where a programming language is used to describe an architecture instance, and then compilation of this generates P4 specs needed to describe (a) the P4 components that will be dropped into the architecture instance; and (b) library methods that will be available for use by the P4 components.  Overall compilation involves generation of a complete system implementation that incorporates implementations of the P4 components.  The approach will be illustrated by a prototype Xilinx compilation flow that generates such systems with an FPGA implementation, given an architecture description and included P4 component descriptions as input.

Speakers
avatar for Gordon Brebner, Xilinx

Gordon Brebner, Xilinx

Dr. Gordon Brebner is a Distinguished Engineer at Xilinx, Inc., the worldwide leader in all-programmable technologies. He works in Xilinx Labs, leading an international group researching issues surrounding networked processing systems of the future. His main personal research interests concern dynamically reconfigurable architectures, domain-specific languages with highly concurrent implementations, and high performance networking and... Read More →



Wednesday November 18, 2015 2:15pm - 2:30pm
McCaw Hall - Presentations

Attendees (3)